1. Field of the Invention
The present invention relates to a precision polishing apparatus and method for very precisely polishing a substrate, such as a semiconductor wafer or the like.
2. Description of the Related Art
Recently, as semiconductor devices tend to have ultrafine patterns and multilayer interconnections, precision polishing apparatuses for very precisely flattening the surfaces of semiconductor wafers of Si, GaAs, InP, SOI (silicon on insulator) or the like, are being demanded. Particularly, chemical mechanical polishing (CMP) apparatuses are known as precision polishing apparatuses for very precisely flattening the surfaces of substrates, such as wafers on which semiconductor devices are formed.
Conventional CMP apparatuses can be classified into two types as shown in FIGS. 7 and 8.
(1) FIG. 7 is a schematic diagram illustrating an external appearance of a polishing processing unit of a CMP apparatus for performing polishing processing in a state in which the surface to be polished of a wafer 100 is downwardly placed.
As shown in FIG. 7, the wafer 100 is held in a state in which its surface to be polished is downwardly placed, and is polished by being pressed against a polishing pad 1011 having a diameter larger than the diameter of the wafer 100 while being rotated. While the wafer 100 is polished, an abrasive (slurry) is dripped onto the upper surface of the polishing pad 1011.
In this type of apparatus, the wafer 100 is held by a wafer chuck 1003, for example, by means of vacuum suction, bonding using wax, a solution or pure water. In order to prevent displacement of the wafer 100, a guide ring 1004 is, in some cases, provided along the outer circumference of the wafer 100. The diameter of the polishing pad 1011 on a table 1001 is 3-5 times the diameter of the wafer 100. A suspension obtained by dispersing fine particles of silicon oxide in an aqueous solution of potassium hydroxide is used as the slurry.
(2) A method has also been proposed in which, as shown in FIG. 8, a wafer 100 is held on a wafer chuck 1103 having a guide ring 1104 and disposed on a wafer table 1101, in a state in which the surface to be polished of the wafer 100 is upwardly placed, and the wafer 100 is polished using a polishing pad 1111 having a diameter smaller than the diameter of the wafer 100.
These polishing apparatuses and methods can polish substrates, such as currently-used 8-inch semiconductor wafers or the like. Recently, however, as semiconductor integrated circuits tend to have fine patterns and adopt wafers having larger diameters, the diameters of wafers are expected to shift from 8 inches to 12 inches.
In order to polish large-diameter wafers, the conventional techniques have the following problems to be solved.
That is, in the apparatus shown in FIG. 7, the size of the polishing apparatus increases as the diameter of the wafer increases.
In the apparatus shown in FIG. 8, much time is required for uniformly polishing the entire surface of the wafer.
In the above-described conventional apparatuses, it is attempted to control the polishing property by optimizing the thickness, elasticity and the like of the polishing pad in order to polish an 8-inch wafer. In this case, however, it is difficult to assure fine adjustment and uniformity of the material of the polishing pad, and therefore, to very precisely polish a wafer having a larger diameter, such as 12 inches.
In particular, the polishing property of the polishing pad is degraded in the course of time. For example, while the life of the polishing pad is as long as hundreds of hours, the polishing property is degraded by tens of % within this time period.
In addition, flexibility is lacking of polishing a plurality of kinds of IC's (integrated circuits) having different chip sizes and different thicknesses and widths of interconnections with a high throughput.